7.4.1 LPDDR4 Layout Guidelines
(Ask a Question)This section describes the routing guidelines for LPDDR4 interface for PolarFire SoC Family. The guidelines are with reference to maximum x32 data width from a signal integrity perspective. It is recommended to evaluate the interface by performing system-level signal integrity simulations. The user is assumed to have knowledge of the memory interface guidelines.
| Clock Signal | Description |
|---|---|
| CK_c/t | Differential clock signals |
| Address and Control Signals | |
| CA [5:0] | Address signals |
| CKE | Clock enable |
| CS | Chip select |
| Reset_n | Memory reset signal |
| ODT | On die termination |
| Data Group Signals | |
| DQ [15:0] | Data signals |
| DMI[1:0] | Data mask signal |
| DQS_c/t [0:1] | Data strobe signals |