7.4.3 Designing LPDDR4 Interface with PolarFire SoC FPGA

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The following figure shows an example design for PolarFire SoC and LPDDR interface. In the example, the LPDDR4 memory is used from Micron and has dual-channel and single-rank with x32 data width.

Figure 7-16. Schematic of PolarFire SoC and LPDDR4 interface

The following figure shows the DQ Bus Routing (Point-to-Point).

Figure 7-17. DQ Bus Routing (Point-to-point)

The following figure shows the Clk routing (Balance Topology).

Figure 7-18. Clk Routing (Balance Topology)

The following figure shows the CA bus routing (balance topology).

Figure 7-19. CA Bus Routing (Balance Topology)

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