2.8.3 Place and Route Pin-Out Rules

Consider the following points during Place and Route:

  • I/O Bridging is allowed.
  • I/Os cannot share a lane with another independent IF.
  • All DQ must be in the same lane.
  • DQS/RWDS must be on the DQ lane on the P side I/O with the DQS function.
  • The N side I/O with the DQS function must not be used. It is re-used internally to create the DQS Gate, and no other signal can be connected to pin.
  • Addr/command/CLK can be placed anywhere. However, if they are placed in the DQ lane, the parameter I{INTERFACE#}R{RANK#}_{IO}_IN_DQ_LANE must be set to one.
  • Asynchronous input can be placed anywhere.
Important:

In the Octal PHY solution the number of DQS must be a multiple of 2. If you do not follow this rule, then RX_DATA_VALID will stay stuck at 1. Another way to formulate it is that the burst length of transaction issue to Octal PHY must be a multiple of 2.