Contents
Introduction
2. Using the RTG4 Two-Port Large SRAM
2.1. Optimization for High Speed or Low Power
2.2. Write Depth/Width and Read Depth/Width
2.3. Single Clock (CLK) or Independent Write and Read Clocks (WCLK, RCLK)
2.4. Write Enable (WEN)
2.5. Read Enable (REN)
2.6. Pipeline for Read Data Output
2.7. Register Enable (RD_EN)
2.8. Synchronous Reset (RD_SRST_N)
2.9. Asynchronous Reset (ARST_N)
2.10. Expose Write Byte Enables (WBYTE_EN)
2.11. Error Correction Code (ECC)
2.12. RD Register Truth Table
3. Internal Configurator Connections
3.1. WEN Connections
3.2. REN Connections
3.3. WD Connections
3.4. RD Logic
3.5. SB_CORRECT and DB_DETECT Logic
4. Caveats for Two-Port Large SRAM Generation
5. Supported Formats
5.1. Intel HEX
5.2. Motorola S-Record
5.3. Write Port Width Alignment
5.3.1. Write Port Widths Aligned on Byte Boundary
5.3.1.1. 32-bit Write Port Width
5.3.1.2. 16-bit Write Port Width
5.3.1.3. 8-bit Write Port Width
5.3.2. Write Port Widths Not Aligned on Byte Boundary
5.3.2.1. 9-bit Write Port Width
5.3.2.2. 4-bit Write Port Width
5.3.3. Specifying Data in Memory File
5.3.3.1. 9-bit Write Port Width
5.3.3.2. 4-bit Write Port Width
6. RAM Content Manager
6.1. Opening and Using RAM Content Manager
6.1.1. Opening RAM Content Manager
6.1.2. RAM Configuration
6.1.3. Write Port View and Read Port View
6.2. MEMFILE (RAM Content Manager Output File)
7. Port Description
8. Parameters
9. Revision History
10. Microchip FPGA Support
The Microchip Website
Product Change Notification Service
Customer Support
Microchip Devices Code Protection Feature
Legal Notice
Trademarks
Quality Management System
Worldwide Sales and Service