48.7.3 SPDIF Transmitter Extended Mode Register
This register can only be written if the WPEN bit is cleared in SPDIFTX_WPMR.
| Name: | SPDIFTX_EMR |
| Offset: | 0x08 |
| Reset: | 0x03000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| VALIDM | PARM | CSM | UDM | PCM | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 4 – VALIDM Validity Bit Mode
| Value | Description |
|---|---|
| 0 | Validity bit is defined by SPDIFTX_MR.VALID1 and SPDIFTX_MR.VALID2 values. |
| 1 | Validity bit is defined by SPDIFTX_CDR.VALID. |
Bit 3 – PARM Parity Mode
| Value | Description |
|---|---|
| 0 | Parity bit is automatically set by the SPDIFTX. |
| 1 | Parity bit sent is defined by SPDIFTX_CDR.PAR. |
Bit 2 – CSM Channel Status Mode
| Value | Description |
|---|---|
| 0 | Channel status is defined by SPDIFTX_CHySx. |
| 1 | Channel status is defined by SPDIFTX_CDR.CS. |
Bit 1 – UDM User Data Mode
| Value | Description |
|---|---|
| 0 | User data is defined by SPDIFTX_CHyUDx. |
| 1 | User data is defined by SPDIFTX_CDR.UD. |
Bit 0 – PCM Preamble Code Mode
| Value | Description |
|---|---|
| 0 | Preamble code is generated automatically by the SPDIFTX. |
| 1 | Preamble code is defined by SPDIFTX_CDR.PC. |