48.7.2 SPDIF Transmitter Mode Register


Bit	31	30	29	28	27	26	25	24
	DUDCPY	DCSCPY	BPS[1:0]		DNFR		VALID2	VALID1
Access	R/W	R/W	R/W	R/W	R/W		R/W	R/W
Reset	0	0	1	0	0		1	1


Bit	23	22	21	20	19	18	17	16
				CHUNK[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	1


Bit	15	14	13	12	11	10	9	8
			VBPS[5:0]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	1	1	0	0	0


Bit	7	6	5	4	3	2	1	0
			CMODE[1:0]		JUSTIFY	ENDIAN	MULTICH	TXEN
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	1	1	0

Bit 31 – DUDCPY Disable User Data Copy

Value	Description
0	Any data written in SPDIFTX_CH1UDx registers is copied to SPDIFTX_CH2UDx.
1	SPDIFTX_CH1UDx and SPDIFTX_CH2UDx are independent.

Bit 30 – DCSCPY Disable Channel Status Copy

Value	Description
0	Any data written in SPDIFTX_CH1Sx registers is copied to SPDIFTX_CH2Sx.
1	SPDIFTX_CH1Sx and SPDIFTX_CH2Sx are independent.

Bits 29:28 – BPS[1:0] Bytes Per Sample

This field defines the SPDIFTX_CDR operating mode by assigning a size to the data container holding each sample. See Data Organization.

Value	Name	Description
0	BYTE1	SPDIFTX_CDR data holding operating mode is optimized for data size up to 8 bits.
1	BYTE2	SPDIFTX_CDR data holding operating mode is optimized for data size in range 9 to 16 bits.
2	BYTE3	SPDIFTX_CDR data holding operating mode is optimized for data size in range 17 to 24 bits.
3	BYTE4	SPDIFTX_CDR data holding operating mode is optimized for data size in range 25 to 32 bits.

Bit 27 – DNFR Disable Null Frame on Underrun

Value	Description
0	In case of underrun (SPDIFTX_ISR.TXEMPTY flag is set and SPDIFTX needs a data), invalid frames are sent (Validity bit at level ‘1’).
1	In case of underrun (SPDIFTX_ISR.TXEMPTY flag is set and SPDIFTX needs a data), valid frames are sent.

Bit 25 – VALID2 Validity Bit Channel 2

Bit 24 – VALID1 Validity Bit Channel 1

Bits 20:16 – CHUNK[4:0] DMA Chunk Size

Defines the size of the chunk performed by the DMA. Refer to the DMA Controller (XDMAC) section for the supported burst length sizes.

The minimum CHUNK value is 1.

The DMA controller transfers must be configured with the same chunk size. Refer to the DMA Controller (XDMAC) section.

TXCHUNK raises when the transmit FIFO has room for CHUNK data (written through SPDIFTX_CDR).

Bits 13:8 – VBPS[5:0] Valid Bits Per Sample

This field is used to explicitly indicate how many bits of precision are present in the signal.

VBPS must be less than or equal to the number of bits of the container defined in SPDIFTX_MR.BPS and must be greater than 1.

If VBPS is less than the number of bits per sample of the container defined by SPDIFTX_MR.BPS, then the data alignment is defined in SPDIFTX_MR.JUSTIFY.

Bits 5:4 – CMODE[1:0] Common Audio Register Transfer Mode (if BPS=2)

CMODE has no effect when SPDIFTX_MR.BPS is not equal to 2.

Value	Name	Description
0	CHANNEL_INDEX	SPDIFTX_CDR.CDR[25:24] indicates the channel on which the data CDR[23:0] will be transmitted (1 for channel 1, 2 for channel 2). Transmitted data are located on SPDIFTX_CDR.CDR[23:0].
1	CHANNELS_TOGGLING	The data are stored alternately in the FIFO of channel 1 and channel 2. The first sent data after a software or hardware reset is stored in the FIFO of channel 1. Transmitted data are located on SPDIFTX_CDR.CDR[23:0].
2	COMPACT_24BIT	This mode is optimized for 24-bit data compacted on a 32-bit memory space. Transmitted data are located on SPDIFTX_CDR.CDR[31:0]. The 32 bits of SPDIFTX_CDR are used and contain one or more channel data.
3	CONTROL_BITS	Control bits (preamble, validity, user data, channel status, parity) can be managed by writing SPDIFTX_CDR.CDR[31:24] depending on SPDIFTX_EMR configuration. The data are stored alternately in the FIFO of channel 1 and channel 2. The first data sent after a software or hardware reset is stored in the FIFO of channel 1. Transmitted data are located on SPDIFTX_CDR.CDR[23:0].

Bit 3 – JUSTIFY Data Justification

Value	Name	Description
0	LSB	Least Significant Bit justification. The valid bits of the signal are aligned on the least-significant bits of the container.
1	MSB	Most Significant Bit justification. The valid bits of the signal are aligned on the most-significant bits of the container.

Bit 2 – ENDIAN Data Word Endian Mode

Value	Name	Description
0	LITTLE	Little-endian mode.
1	BIG	Big-endian mode.

Bit 1 – MULTICH Multichannel Transfer

Value	Name	Description
0	MONO	One channel is sent on channel 1 to SPDIFTX_TX and is copied on channel 2.
1	DUAL	Two separate channels are sent to SPDIFTX_TX.

Bit 0 – TXEN SPDIFTX Transmit Enable

Value	Name	Description
0	DISABLE	SPDIFTX transmission is disabled.
1	ENABLE	SPDIFTX transmission is enabled.

Name:	SPDIFTX_MR
Offset:	0x04
Reset:	0x23011806
Property:	Read/Write