48.7.4 SPDIF Transmitter Common Data Register
| Name: | SPDIFTX_CDR |
| Offset: | 0x0C |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CDR[31:24] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CDR[23:16] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CDR[15:8] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CDR[7:0] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – | |
Bits 31:0 – CDR[31:0] Common Data Register
Data sent to channel 1 and/or channel 2.
The mapping of the register depends on the transfer configuration defined in SPDIFTX_MR.