48.7.10 SPDIF Transmitter Interrupt Status Register
| Name: | SPDIFTX_ISR |
| Offset: | 0x20 |
| Reset: | 0x000000CB |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| BEND | SECE | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| UDRDY | CSRDY | TXOVR | TXUDR | TXCHUNK | TXFULL | TXEMPTY | TXRDY | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 |
Bit 13 – BEND Block End Status (cleared on read)
| Value | Description |
|---|---|
| 0 | No Block End event occurred since the last read of SPDIFTX_ISR. |
| 1 | At least one Block End event occurred since the last read of SPDIFTX_ISR. |
Bit 10 – SECE Security Report Status (cleared on read)
| Value | Description |
|---|---|
| 0 | There is no security report in SPDIFTX_WPSR. |
| 1 | One security flag is set in SPDIFTX_WPSR. |
Bit 7 – UDRDY User Data Ready Status (cleared by writing SPDIFTX_CHyUDR0 register)
| Value | Description |
|---|---|
| 0 | SPDIFTX_CHyUDx register cannot accept data. |
| 1 | A data can be written to SPDIFTX_CHyUDx. |
Bit 6 – CSRDY Channel Status Ready Status (cleared by writing SPDIFTX_CHyS0 register)
| Value | Description |
|---|---|
| 0 | SPDIFTX_CHySx register cannot accept data. |
| 1 | A data can be written to SPDIFTX_CHySx. |
Bit 5 – TXOVR Transmit Over Flow Status (cleared on read)
| Value | Description |
|---|---|
| 0 | No Transmit FIFO overflow occurred since last read of SPDIFTX_ISR. |
| 1 | A data has been written while the transmit FIFO was full. |
Bit 4 – TXUDR Transmit Under Flow Status (cleared on read)
| Value | Description |
|---|---|
| 0 | All transmit FIFOs has been filled on time. |
| 1 | One of the Transmit FIFOs has not been filled on time. |
Bit 3 – TXCHUNK Transmit FIFO Chunk Size Empty Status (cleared by writing CHUNK data in SPDIFTX_CDR)
| Value | Description |
|---|---|
| 0 | The TX FIFOs cannot accept SPDIFTX_MR.CHUNK data transfer through SPDIFTX_CDR. |
| 1 | The TX FIFOs can accept SPDIFTX_MR.CHUNK data transfer through SPDIFTX_CDR. |
Bit 2 – TXFULL Transmit FIFO Full Status (cleared when data are sent or writing SPDIFTX_CR.FCLR)
| Value | Description |
|---|---|
| 0 | Transmit FIFOs are not full. |
| 1 | Transmit FIFOs are full. |
Bit 1 – TXEMPTY Transmit FIFO Empty Status (cleared by writing SPDIFTX_CDR)
| Value | Description |
|---|---|
| 0 | Transmit FIFOs are not empty. |
| 1 | Transmit FIFOs are empty. |
Bit 0 – TXRDY Transmit Ready Status (cleared when both channel 1 and 2 FIFOs are full)
| Value | Description |
|---|---|
| 0 | Transmit FIFOs are full and cannot accept more data |
| 1 | Transmit FIFOs are not full; one data can be written to SPDIFTX_CDR |