48.7.5 SPDIF Transmitter Common Data Register (CONTROL_BITS)
| Name: | SPDIFTX_CDR (CONTROL_BITS) |
| Offset: | 0x0C |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| PC[1:0] | PAR | CS | UD | VALID | |||||
| Access | W | W | W | W | W | W | |||
| Reset | – | – | – | – | – | – | |||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CDR[23:16] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CDR[15:8] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CDR[7:0] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – | |
Bits 29:28 – PC[1:0] Preamble Code
| Value | Name | Description |
|---|---|---|
| 0 | PREAMBLE_B | Preamble “B” is sent. |
| 1 | PREAMBLE_M | Preamble “M” is sent. |
| 2 | PREAMBLE_W | Preamble “W” is sent. |
Bit 27 – PAR Parity
| Value | Description |
|---|---|
| 0 | Correct parity bit is sent. |
| 1 | Wrong parity bit is sent. |
Bit 26 – CS Channel Status
Bit 25 – UD User Data
Bit 24 – VALID Validity Bit
| Value | Description |
|---|---|
| 0 | Sample is valid for analog conversion. |
| 1 | Sample is not valid for analog conversion. |
Bits 23:0 – CDR[23:0] Common Data Register
Data sent to channel 1 and/or channel 2.
The mapping of the register depends on the transfer configuration defined in SPDIFTX_MR.