72.10 UDPHS Endpoint Control Enable Register (Isochronous Endpoints)
This register view is relevant only if UDPHS_EPTCFGx.EPT_TYPE = 0x1.
For additional information, see UDPHS_EPTCTLx.
| Name: | UDPHS_EPTCTLENBx |
| Offset: | 0x0104 + x*0x20 [x=0..15] |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SHRT_PCKT | |||||||||
| Access | W | ||||||||
| Reset | – |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| BUSY_BANK | |||||||||
| Access | W | ||||||||
| Reset | – |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ERR_FLUSH | ERR_CRC_NTR | ERR_FL_ISO | TXRDY_TRER | TX_COMPLT | RXRDY_TXKL | ERR_OVFLW | |||
| Access | W | W | W | W | W | W | W | ||
| Reset | – | – | – | – | – | – | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MDATA_RX | DATAX_RX | INTDIS_DMA | AUTO_VALID | EPT_ENABL | |||||
| Access | W | W | W | W | W | ||||
| Reset | – | – | – | – | – |
Bit 31 – SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable
For IN endpoints: Ensures short packet at end of DMA Transfer if the UDPHS_DMACONTROLx register END_B_EN and UDPHS_EPTCTLx register AUTOVALID bits are also set.
For OUT endpoints:
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enable Short Packet Interrupt. |
Bit 18 – BUSY_BANK Busy Bank Interrupt Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enable Busy Bank Interrupt. |
Bit 14 – ERR_FLUSH Bank Flush Error Interrupt Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enable Bank Flush Error Interrupt. |
Bit 13 – ERR_CRC_NTR ISO CRC Error/Number of Transaction Error Interrupt Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enable Error CRC ISO/Error Number of Transaction Interrupt. |
Bit 12 – ERR_FL_ISO Error Flow Interrupt Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enable Error Flow ISO Interrupt. |
Bit 11 – TXRDY_TRER TX Packet Ready/Transaction Error Interrupt Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enable TX Packet Ready/Transaction Error Interrupt. |
Bit 10 – TX_COMPLT Transmitted IN Data Complete Interrupt Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enable Transmitted IN Data Complete Interrupt. |
Bit 9 – RXRDY_TXKL Received OUT Data Interrupt Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enable Received OUT Data Interrupt. |
Bit 8 – ERR_OVFLW Overflow Error Interrupt Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enable Overflow Error Interrupt. |
Bit 7 – MDATA_RX MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enable MDATA Interrupt. |
Bit 6 – DATAX_RX DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints)
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enable DATAx Interrupt. |
Bit 3 – INTDIS_DMA Interrupts Disable DMA
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled. |
Bit 1 – AUTO_VALID Packet Auto-Valid Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enable this bit to automatically validate the current packet and switch to the next bank for both IN and OUT transfers. |
Bit 0 – EPT_ENABL Endpoint Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enable endpoint according to the device configuration. |