72.9 UDPHS Endpoint Control Enable Register (Control, Bulk, Interrupt Endpoints) (Default Mode)

This register view is relevant only if UDPHS_EPTCFGx.EPT_TYPE = 0x0, 0x2 or 0x3.

For additional information, see UDPHS_EPTCTLx.

Name: UDPHS_EPTCTLENBx (DEFAULT_MODE)
Offset: 0x0104 + n*0x20 [n=0..15]
Reset: 
Property: Write-only

Bit 3130292827262524 
 SHRT_PCKT        
Access W 
Reset  
Bit 2322212019181716 
      BUSY_BANK   
Access W 
Reset  
Bit 15141312111098 
 NAK_OUTNAK_INSTALL_SNTRX_SETUPTXRDYTX_COMPLTRXRDY_TXKLERR_OVFLW 
Access WWWWWWWW 
Reset  
Bit 76543210 
    NYET_DISINTDIS_DMA AUTO_VALIDEPT_ENABL 
Access WWWW 
Reset  

Bit 31 – SHRT_PCKT Short Packet Send/Short Packet Interrupt Enable

For IN endpoints: Ensures short packet at end of DMA Transfer if the UDPHS_DMACONTROLx register END_B_EN and UDPHS_EPTCTLx register AUTOVALID bits are also set.

For OUT endpoints:

ValueDescription
0

No effect.

1

Enable Short Packet Interrupt.

Bit 18 – BUSY_BANK Busy Bank Interrupt Enable

ValueDescription
0

No effect.

1

Enable Busy Bank Interrupt.

Bit 15 – NAK_OUT NAKOUT Interrupt Enable

ValueDescription
0

No effect.

1

Enable NAKOUT Interrupt.

Bit 14 – NAK_IN NAKIN Interrupt Enable

ValueDescription
0

No effect.

1

Enable NAKIN Interrupt.

Bit 13 – STALL_SNT Stall Sent Interrupt Enable

ValueDescription
0

No effect.

1

Enable Stall Sent Interrupt.

Bit 12 – RX_SETUP Received SETUP

ValueDescription
0

No effect.

1

Enable RX_SETUP Interrupt.

Bit 11 – TXRDY TX Packet Ready Interrupt Enable

ValueDescription
0

No effect.

1

Enable TX Packet Ready/Transaction Error Interrupt.

Bit 10 – TX_COMPLT Transmitted IN Data Complete Interrupt Enable

ValueDescription
0

No effect.

1

Enable Transmitted IN Data Complete Interrupt.

Bit 9 – RXRDY_TXKL Received OUT Data Interrupt Enable

ValueDescription
0

No effect.

1

Enable Received OUT Data Interrupt.

Bit 8 – ERR_OVFLW Overflow Error Interrupt Enable

ValueDescription
0

No effect.

1

Enable Overflow Error Interrupt.

Bit 4 – NYET_DIS NYET Disable (Only for High Speed Bulk OUT endpoints)

ValueDescription
0

No effect.

1

Forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response.

Bit 3 – INTDIS_DMA Interrupts Disable DMA

ValueDescription
0

No effect.

1

If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled.

Bit 1 – AUTO_VALID Packet Auto-Valid Enable

ValueDescription
0

No effect.

1

Enable this bit to automatically validate the current packet and switch to the next bank for both IN and OUT transfers.

Bit 0 – EPT_ENABL Endpoint Enable

ValueDescription
0

No effect.

1

Enable endpoint according to the device configuration.