72.15 UDPHS Endpoint Set Status Register (Control, Bulk, Interrupt Endpoints) (Default Mode)

This register view is relevant only if UDPHS_EPTCFGx.EPT_TYPE = 0x0, 0x2 or 0x3.

For additional information, see UDPHS_EPTSTAx.

Name: UDPHS_EPTSETSTAx (DEFAULT_MODE)
Offset: 0x0114 + n*0x20 [n=0..15]
Reset: 
Property: Write-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
     TXRDY RXRDY_TXKL  
Access WW 
Reset  
Bit 76543210 
   FRCESTALL      
Access W 
Reset  

Bit 11 – TXRDY TX Packet Ready Set

ValueDescription
0

No effect.

1

Set this bit after a packet has been written into the endpoint FIFO for IN data transfers

– This flag is used to generate a Data IN transaction (device to host).

– Device firmware checks that it can write a data payload in the FIFO, checking that TXRDY is cleared.

– Transfer to the FIFO is done by writing in the “Buffer Address” register.

– Once the data payload has been transferred to the FIFO, the firmware notifies the UDPHS device setting TXRDY to one.

– UDPHS bus transactions can start.

– TXCOMP is set once the data payload has been received by the host.

– Data should be written into the endpoint FIFO only after this bit has been cleared.

– Set this bit without writing data to the endpoint FIFO to send a Zero Length Packet.

Bit 9 – RXRDY_TXKL KILL Bank Set (for IN Endpoint)

ValueDescription
0

No effect.

1

Kill the last written bank.

Bit 5 – FRCESTALL Stall Handshake Request Set

Refer to chapters 8.4.5 (Handshake Packets) and 9.4.5 (Get Status) of the Universal Serial Bus Specification, Rev 2.0 for more information on the STALL handshake.

ValueDescription
0

No effect.

1

Set this bit to request a STALL answer to the host for the next handshake