72.16 UDPHS Endpoint Set Status Register (Isochronous Endpoint)
This register view is relevant only if UDPHS_EPTCFGx.EPT_TYPE = 0x1.
For additional information, see UDPHS_EPTSTAx.
| Name: | UDPHS_EPTSETSTAx |
| Offset: | 0x0114 + x*0x20 [x=0..15] |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TXRDY_TRER | RXRDY_TXKL | ||||||||
| Access | W | W | |||||||
| Reset | – | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |
Bit 11 – TXRDY_TRER TX Packet Ready Set
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Set this bit after a packet has been written into the endpoint FIFO for IN data transfers – This flag is used to generate a Data IN transaction (device to host). – Device firmware checks that it can write a data payload in the FIFO, checking that TXRDY_TRER is cleared. – Transfer to the FIFO is done by writing in the “Buffer Address” register. – Once the data payload has been transferred to the FIFO, the firmware notifies the UDPHS device setting TXRDY_TRER to one. – UDPHS bus transactions can start. – TXCOMP is set once the data payload has been sent. – Data should be written into the endpoint FIFO only after this bit has been cleared. – Set this bit without writing data to the endpoint FIFO to send a Zero Length Packet. |
Bit 9 – RXRDY_TXKL KILL Bank Set (for IN Endpoint)
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Kill the last written bank. |