72.19 UDPHS Endpoint Status Register (Control, Bulk, Interrupt Endpoints) (Default Mode)

This register view is relevant only if UDPHS_EPTCFGx.EPT_TYPE = 0x0, 0x2 or 0x3.

Name: UDPHS_EPTSTAx (DEFAULT_MODE)
Offset: 0x011C + n*0x20 [n=0..15]
Reset: 0x00000040
Property: Read-only

Bit 3130292827262524 
 SHRT_PCKTBYTE_COUNT[10:4] 
Access RRRRRRRR 
Reset 00000000 
Bit 2322212019181716 
 BYTE_COUNT[3:0]BUSY_BANK_STA[1:0]CURBK_CTLDIR[1:0] 
Access RRRRRRRR 
Reset 00000000 
Bit 15141312111098 
 NAK_OUTNAK_INSTALL_SNTRX_SETUPTXRDYTX_COMPLTRXRDY_TXKLERR_OVFLW 
Access RRRRRRRR 
Reset 00000000 
Bit 76543210 
 TOGGLESQ_STA[1:0]FRCESTALL      
Access RRR 
Reset 010 

Bit 31 – SHRT_PCKT Short Packet (cleared upon USB reset)

An OUT Short Packet is detected when the receive byte count is less than the configured UDPHS_EPTCFGx register EPT_Size.

This bit is updated at the same time as the BYTE_COUNT field.

It is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).

Bits 30:20 – BYTE_COUNT[10:0] UDPHS Byte Count (cleared upon USB reset)

Byte count of a received data packet.

This field is incremented after each write into the endpoint (to prepare an IN transfer). It is decremented after each reading into the endpoint (OUT transfer).

This field is also updated at RXRDY_TXKL flag clear with the next bank, and at TXRDY flag set with the next bank.

This field is reset by UDPHS_EPTRST.EPT_x.

Bits 19:18 – BUSY_BANK_STA[1:0] Busy Bank Number (cleared upon USB reset)

These bits are set by hardware to indicate the number of busy banks.

IN endpoint: Indicates the number of busy banks filled by the user, ready for IN transfer.

OUT endpoint: Indicates the number of busy banks filled by OUT transaction from the Host.

ValueNameDescription
0 0BUSYBANK

All banks are free

1 1BUSYBANK

1 busy bank

2 2BUSYBANKS

2 busy banks

3 3BUSYBANKS

3 busy banks

Bits 17:16 – CURBK_CTLDIR[1:0] Current Bank/Control Direction (cleared upon USB reset)

Control Direction (for Control endpoint only):

0: A Control Write is requested by the Host.

1: A Control Read is requested by the Host.
Note:
  1. Corresponds to the the 7th bit of the bmRequestType (Byte 0 of the Setup Data).
  2. Updated after receiving new setup data.
Current Bank (not relevant for Control endpoint):
  • Set by hardware to indicate the number of the current bank.
  • Reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
  • The current bank is updated each time the user:

    • Sets the TX Packet Ready bit to prepare the next IN transfer and to switch to the next bank.

    • Clears the received OUT data bit to access the next bank.
ValueNameDescription
0 BANK0

Bank 0 (or single bank)

1 BANK1

Bank 1

2 BANK2

Bank 2

Bit 15 – NAK_OUT NAK OUT (cleared upon USB reset)

This bit is set by hardware when a NAK handshake has been sent in response to an OUT or PING request from the Host.

This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by EPT_CTL_DISx (disable endpoint).

Bit 14 – NAK_IN NAK IN (cleared upon USB reset)

This bit is set by hardware when a NAK handshake has been sent in response to an IN request from the Host.

This bit is cleared by software.

Bit 13 – STALL_SNT Stall Sent (cleared upon USB reset)

For Control, Bulk and Interrupt endpoints.

This bit is set by hardware after a STALL handshake has been sent as requested by the UDPHS_EPTSTAx register FRCESTALL bit.

This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).

Bit 12 – RX_SETUP Received SETUP (cleared upon USB reset)

For Control endpoint only.

This bit is set by hardware when a valid SETUP packet has been received from the host.

It is cleared by the device firmware after reading the SETUP data from the endpoint FIFO.

This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable endpoint).

Bit 11 – TXRDY TX Packet Ready (cleared upon USB reset)

This bit is cleared by hardware after the host has acknowledged the packet.

For Multi-bank endpoints, this bit may remain clear even after software is set if another bank is available to transmit.

Hardware clear of this bit may generate an interrupt if enabled by the UDPHS_EPTCTLx register TXRDY bit.

This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable endpoint).

Bit 10 – TX_COMPLT Transmitted IN Data Complete (cleared upon USB reset)

This bit is set by hardware after an IN packet has been accepted (ACK’ed) by the host.

This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable endpoint).

Bit 9 – RXRDY_TXKL Received OUT Data/KILL Bank (cleared upon USB reset)

Received OUT Data (for OUT endpoint or Control endpoint):
  • This bit is set by hardware after a new packet has been stored in the endpoint FIFO.
  • This bit is cleared by the device firmware after reading the OUT data from the endpoint.
  • For multi-bank endpoints, this bit may remain active even when cleared by the device firmware, this if an other packet has been received meanwhile.
  • Hardware assertion of this bit may generate an interrupt if enabled by the UDPHS_EPTCTLx register RXRDY_TXKL bit.
  • This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
KILL Bank (for IN endpoint):
  • The bank is really cleared or the bank is sent, BUSY_BANK_STA is decremented.
  • The bank is not cleared but sent on the IN transfer, TX_COMPLT
  • The bank is not cleared because it was empty. The user should wait that this bit is cleared before trying to clear another packet.
    Note: “Kill a packet” may be refused if at the same time, an IN token is coming and the current packet is sent on the UDPHS line. In this case, the TX_COMPLT bit is set. Take notice however, that if at least two banks are ready to be sent, there is no problem to kill a packet even if an IN token is coming. In fact, in that case, the current bank is sent (IN transfer) and the last bank is killed.

Bit 8 – ERR_OVFLW Overflow Error (cleared upon USB reset)

This bit is set by hardware when a new too-long packet is received.

Example: If the user programs an endpoint 64 bytes wide and the host sends 128 bytes in an OUT transfer, then the Overflow Error bit is set.

This bit is updated at the same time as the BYTE_COUNT field.

This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).

Bits 7:6 – TOGGLESQ_STA[1:0] Toggle Sequencing (cleared upon USB reset)

In OUT transfer, the Toggle information is meaningful only when the current bank is busy (Received OUT Data = 1).

This field is updated for OUT transfer: 


  • A new data has been written into the current bank.

  • The user has just cleared the Received OUT Data bit to switch to the next bank.

This field is reset to DATA1 by the UDPHS_EPTCLRSTAx register TOGGLESQ bit, and by UDPHS_EPTCTLDISx (disable endpoint).

Toggle Sequencing:

  • IN endpoint: Indicates the PID Data Toggle that will be used for the next packet sent. This is not relative to the current bank.
  • CONTROL and OUT endpoints: Set by hardware to indicate the PID data of the current bank.
ValueNameDescription
0 DATA0

DATA0

1 DATA1

DATA1

2 DATA2

Reserved for High Bandwidth Isochronous Endpoint

3 MDATA

Reserved for High Bandwidth Isochronous Endpoint

Bit 5 – FRCESTALL Stall Handshake Request (cleared upon USB reset)

This bit is reset by hardware upon received SETUP.

ValueDescription
0

No effect.

1

If set a STALL answer will be done to the host for the next handshake.