72.17 UDPHS Endpoint Clear Status Register (Control, Bulk, Interrupt Endpoints) (Default Mode)

This register view is relevant only if UDPHS_EPTCFGx.EPT_TYPE = 0x0, 0x2 or 0x3.

For additional information, see UDPHS_EPTSTAx.

Name: UDPHS_EPTCLRSTAx (DEFAULT_MODE)
Offset: 0x0118 + n*0x20 [n=0..15]
Reset: –
Property: Write-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
 NAK_OUTNAK_INSTALL_SNTRX_SETUP TX_COMPLTRXRDY_TXKL  
Access WWWWWW 
Reset –––––– 
Bit 76543210 
  TOGGLESQFRCESTALL      
Access WW 
Reset –– 

Bit 15 – NAK_OUT NAKOUT Clear

ValueDescription
0

No effect.
1

Clear the NAK_OUT flag of UDPHS_EPTSTAx.

Bit 14 – NAK_IN NAKIN Clear

ValueDescription
0

No effect.
1

Clear the NAK_IN flags of UDPHS_EPTSTAx.

Bit 13 – STALL_SNT Stall Sent Clear

ValueDescription
0

No effect.
1

Clear the STALL_SNT flags of UDPHS_EPTSTAx.

Bit 12 – RX_SETUP Received SETUP Clear

ValueDescription
0

No effect.
1

Clear the RX_SETUP flags of UDPHS_EPTSTAx.

Bit 10 – TX_COMPLT Transmitted IN Data Complete Clear

ValueDescription
0

No effect.
1

Clear the TX_COMPLT flag of UDPHS_EPTSTAx.

Bit 9 – RXRDY_TXKL Received OUT Data Clear

ValueDescription
0

No effect.
1

Clear the RXRDY_TXKL flag of UDPHS_EPTSTAx.

Bit 6 – TOGGLESQ Data Toggle Clear

For OUT endpoints, the next received packet should be a DATA0.

For IN endpoints, the next packet will be sent with a DATA0 PID.

ValueDescription
0

No effect.
1

Clear the PID data of the current bank

Bit 5 – FRCESTALL Stall Handshake Request Clear

ValueDescription
0

No effect.
1

Clear the STALL request. The next packets from host will not be STALLed.