72.5 UDPHS Clear Interrupt Register
| Name: | UDPHS_CLRINT |
| Offset: | 0x18 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| UPSTR_RES | ENDOFRSM | WAKE_UP | ENDRESET | INT_SOF | MICRO_SOF | DET_SUSPD | |||
| Access | W | W | W | W | W | W | W | ||
| Reset | – | – | – | – | – | – | – |
Bit 7 – UPSTR_RES Upstream Resume Interrupt Clear
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Clear the UPSTR_RES bit in UDPHS_INTSTA. |
Bit 6 – ENDOFRSM End Of Resume Interrupt Clear
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Clear the ENDOFRSM bit in UDPHS_INTSTA. |
Bit 5 – WAKE_UP Wake Up CPU Interrupt Clear
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Clear the WAKE_UP bit in UDPHS_INTSTA. |
Bit 4 – ENDRESET End Of Reset Interrupt Clear
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Clear the ENDRESET bit in UDPHS_INTSTA. |
Bit 3 – INT_SOF Start Of Frame Interrupt Clear
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Clear the INT_SOF bit in UDPHS_INTSTA. |
Bit 2 – MICRO_SOF Micro Start Of Frame Interrupt Clear
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Clear the MICRO_SOF bit in UDPHS_INTSTA. |
Bit 1 – DET_SUSPD Suspend Interrupt Clear
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Clear the DET_SUSPD bit in UDPHS_INTSTA. |