72.18 UDPHS Endpoint Clear Status Register (Isochronous Endpoint)
This register view is relevant only if UDPHS_EPTCFGx.EPT_TYPE = 0x1.
For additional information, see UDPHS_EPTSTAx.
| Name: | UDPHS_EPTCLRSTAx |
| Offset: | 0x0118 + x*0x20 [x=0..15] |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ERR_FLUSH | ERR_CRC_NTR | ERR_FL_ISO | TX_COMPLT | RXRDY_TXKL | |||||
| Access | W | W | W | W | W | ||||
| Reset | – | – | – | – | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TOGGLESQ | |||||||||
| Access | W | ||||||||
| Reset | – |
Bit 14 – ERR_FLUSH Bank Flush Error Clear
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Clear the ERR_FLUSH flags of UDPHS_EPTSTAx. |
Bit 13 – ERR_CRC_NTR Number of Transaction Error Clear
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Clear the ERR_CRC_NTR flags of UDPHS_EPTSTAx. |
Bit 12 – ERR_FL_ISO Error Flow Clear
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Clear the ERR_FL_ISO flags of UDPHS_EPTSTAx. |
Bit 10 – TX_COMPLT Transmitted IN Data Complete Clear
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Clear the TX_COMPLT flag of UDPHS_EPTSTAx. |
Bit 9 – RXRDY_TXKL Received OUT Data Clear
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Clear the RXRDY_TXKL flag of UDPHS_EPTSTAx. |
Bit 6 – TOGGLESQ Data Toggle Clear
For OUT endpoints, the next received packet should be a DATA0.
For IN endpoints, the next packet will be sent with a DATA0 PID.
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Clear the PID data of the current bank |