74.7.11 PLL Characteristics

The following characteristics apply to CPUPLL, DDRPLL, IMGPLL, SYSPLL, BAUDPLL, AUDIOPLL and ETHPLL and are provided for register PMC_PLL_ACR programmed to the recommended value 0x00070010.

Table 74-58. PLL Characteristics
Symbol	Parameter	Conditions	Min	Max	Unit
V_DDIN33	Supply voltage range (VDDIN33) ⁽¹⁾	–	3.0	3.6	V
V_DDCORE	Supply voltage range (VDDCORE)	–	1.12	1.21	V
I_VDDIN33	Current consumption (VDDIN33)⁽²⁾	f_COREPLLCK = 1.0 GHz	–	2.9	mA
I_VDDCORE	Current consumption (VDDCORE)⁽²⁾	f_COREPLLCK = 1.0 GHz	–	3.5	mA
t_START	Start-up time⁽²⁾	To reach 95% of target frequency	–	50	μs
f_IN	Input frequency range	–	10	50	MHz
f_COREPLLCK	COREPLLCK frequency range	–	600	1200	MHz
f_IOPLLCK	IOPLLCK⁽³⁾ frequency range	–	–	100	MHz

Note:

The PLLs are powered by the 2.5V regulated output, which is supplied from VDDIN33.
Simulation data
IOPLLCK is available on the AUDIOPLL only and corresponds to the AUDIOCLK pin.

Table 74-59. PLL Output Clocks Characteristics
Symbol	Parameter⁽¹⁾	Conditions	Min	Max	Unit
f_CPUPLLCK	CPUPLLCK frequency range	–	–	1000	MHz
f_DDRPLLCK	DDRPLLCK frequency range	–	–	533	MHz
f_IMGPLLCK	IMGPLLCK frequency range	–	–	266	MHz
f_SYSPLLCK	SYSPLLCK frequency range	–	–	416	MHz
f_BAUDPLLCK	BAUDPLLCK frequency range	–	–	208	MHz
f_AUDIOPLLCK	AUDIOPLLCK frequency range	–	–	200	MHz
f_ETHPLLCK	ETHPLLCK frequency range	–	–	125	MHz

Note:

Simulation data

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