74.7.13 12-bit ADC Characteristics

Table 74-61. ADC Power Supply and Voltage Reference Input Characteristics
Symbol Parameter Conditions Min Max Unit
VDDIN33 Supply voltage range (VDDIN33)(1) – 3.0 3.6 V
IVDDIN33 Current consumption on VDDIN33(1)(2) Low speed (fS ≤ 500 kS/s

ADC_ACR.IBCTL = (00)2)

 – 1.0 mA
Full speed (fS ≤ 1 MS/s

ADC_ACR.IBCTL = (01)2)

 – 1.8 mA
VADVREFP ADVREFP input voltage range – 2.4 2.55 V
RADVREFP ADVREFP input resistance to ground(2) ADC off 7.2 12 kΩ
ADC on 1 – MΩ
CADVREFP Recommended decoupling capacitor on ADVREFP – 1 – μF
Note:
  1. The 12-bit ADC is powered by the VDDOUT25 regulator, which is supplied from VDDIN33.
  2. Simulation data
Table 74-62. ADC Timing Characteristics
Symbol Parameter Conditions Min Max Unit
fCKADC ADC clock frequency ADC_ACR.IBCTL = (00)2 0.1 10 MHz
ADC_ACR.IBCTL = (01)2 0.2 20 MHz
tCONV ADC conversion time(1) – 20 – tCKADC
fS Sampling rate(2) ADC_ACR.IBCTL = (00)2 – 0.5 MS/s
ADC_ACR.IBCTL = (01)2 – 1 MS/s
tSTART Start-up time(3) From Off to On – 5 μs
tTRACK Track and hold time(3)(4) – 300 – ns
Note:
  1. tCONV = tCH + tTRACK + 14 x tCKADC with tCKADC = 1 / fCKADC. The parameter tCH = 0 when the ADC operates in the same input mode (single-ended, pseudo-differential or differential) for the current conversion than for the previous one. tCH = 2 when the ADC input mode is changed to perform the current conversion.
  2. fS = 1 / tCONV
  3. Simulation data
  4. See Track and Hold Time versus Source Impedance – Sampling Rate.
Table 74-63. ADC Analog Input Characteristics
Symbol Parameter Conditions Min Max Unit
VFS Analog input full scale range(1) ADC_CCR.DIFFx = 0 0 VADVREFP V
ADC_CCR.DIFFx = 1 -VADVREFP VADVREFP V
VINCM Common mode input range in Differential Input mode(2) ADC_CCR.DIFFx = 1 0.4 x VDDANA 0.6 x VDDANA V
CS ADC sampling capacitance(3) – – 3 pF
CP_ADx ADx input parasitic capacitance(3)(4) ADx pin configured as analog input – 7 pF
RON Internal series resistor(3)(4) – – 2 kΩ
ZIN Common mode input impedance(3)(5) On ADx pin 1 / (fS x CS) – Ω
RCH30 VBAT resistive attenuator impedance – 80 120 kΩ
GCH30 VBAT channel gain – 0.595 0.605 –
Note:
  1. VFS = (VADx - VGNDANA) in Single-ended mode, VFS = (VADx - VAD11) in Pseudo-differential mode, and VFS = (VADx - VADx+1) in Differential mode
  2. VINCM = (VADx + VADx+1) / 2
  3. Simulation data
  4. With respect to the equivalent model of the figure Equivalent Model of the Acquisition Path
  5. Assuming conversion on one single channel
Figure 74-46. Acquisition Path Block diagram

For tracking time calculation, during the sampling phase of the converter, this acquisition path can be reduced to the equivalent model of the following figure, where:

  • RON = RMUX + RS
  • CP_ADX = CPX + CP_MUX
Figure 74-47. Equivalent Model of the Acquisition Path

See Track and Hold Time versus Source Impedance – Sampling Rate for further details on the use of this model.

In the following table, unless otherwise specified, the specifications are provided for two speed operating ranges.

  • Source resistance = 50 Ω
  • ADC_EMR.OSR<2:0> = (000)2
  • Low-speed
    • fCKADC = 10 MHz, fS = 500 kS/s
    • ADC_ACR.IBCTL = (00)2
  • High-speed
    • fCKADC = 20 MHz, fS = 1 MS/s
    • ADC_ACR.IBCTL = (01)2
Table 74-64. Static Performance Characteristics(1)
Symbol Parameter Min Max Unit
RESADC Native ADC resolution 12 Bit
INL Integral non-linearity -3 3 LSB
DNL Differential non-linearity -2 2 LSB
OE Offset error(2) -4 4 LSB
GE Gain error(2) -4 4 LSB
Note:
  1. In this table, errors are expressed in LSB where:
    • LSB = VVREFP / 212 in Single-ended mode (ADC_CCR.DIFFx = 0)
    • LSB = VVREFP / 211 in Differential or Pseudo-differential mode (ADC_CCR.DIFFx = 1)
  2. Error with respect to the best fit line method.