45.7.8 I2SMCC Interrupt Status Register A

When I2SMCC_MRB.FIFOEN = 1, RXLRDYx, RXRRDYx, TXLRDYx and TXRRDYx are not relevant. See I2SMCC_ISRB.
Name: I2SMCC_ISRA
Offset: 0x1C
Reset: 0x00000003
Property: Read-only

Bit 3130292827262524 
 RXROVF3RXLOVF3RXROVF2RXLOVF2RXROVF1RXLOVF1RXROVF0RXLOVF0 
Access RRRRRRRR 
Reset 00000000 
Bit 2322212019181716 
 RXRRDY3RXLRDY3RXRRDY2RXLRDY2RXRRDY1RXLRDY1RXRRDY0RXLRDY0 
Access RRRRRRRR 
Reset 00000000 
Bit 15141312111098 
 TXRUNF3TXLUNF3TXRUNF2TXLUNF2TXRUNF1TXLUNF1TXRUNF0TXLUNF0 
Access RRRRRRRR 
Reset 00000000 
Bit 76543210 
 TXRRDY3TXLRDY3TXRRDY2TXLRDY2TXRRDY1TXLRDY1TXRRDY0TXLRDY0 
Access RRRRRRRR 
Reset 00000011 

Bits 25, 27, 29, 31 – RXROVFx  I2S Receive Right x or TDM Channel [2x]+1 Overrun Flag (Cleared on read)

ValueDescription
0

Cleared when I2SMCC_ISRA is read.

1

Set when an overrun error occurs in either I2SMCC_RHRxR or I2SMCC_RHR.

Bits 24, 26, 28, 30 – RXLOVFx  I2S Receive Left x or TDM Channel 2x Overrun Flag (Cleared on read)

ValueDescription
0

Cleared when I2SMCC_ISRA is read.

1

Set when an overrun error occurs in either I2SMCC_RHLxR or I2SMCC_RHR.

Bits 17, 19, 21, 23 – RXRRDYx  I2S Receive Right x or TDM Channel [2x]+1 Ready Flag (Cleared by reading I2SMCC_RHR/RHLxR)

ValueDescription
0 Cleared when a predefined number of read accesses are performed in I2SMCC_RHRxR or I2SMCC_RHR. The predefined number depends on the configuration of I2SMCC_MRA.WIRECFG / FORMAT and varies from 1 to 8.
1 Set when received data is available in either I2SMCC_RHRxR or I2SMCC_RHR.

Bits 16, 18, 20, 22 – RXLRDYx  I2S Receive Left x or TDM Channel 2x Ready Flag (Cleared by reading I2SMCC_RHR/RHLxR)

ValueDescription
0

Cleared when a predefined number of read accesses is performed in either I2SMCC_RHLxR or I2SMCC_RHR. The predefined number depends on the configuration of I2SMCC_MRA.WIRECFG/FORMAT and varies from 1 to 7.

1

Set when received data is available in either I2SMCC_RHLxR or I2SMCC_RHR.

Bits 9, 11, 13, 15 – TXRUNFx  I2S Transmit Right x or TDM Channel [2x]+1 Underrun Flag (Cleared on read)

ValueDescription
0

Cleared when the I2SMCC_ISRA is read.

1

Set when an underrun error occurs in either I2SMCC_THR or I2SMCC_THRxR.

Bits 8, 10, 12, 14 – TXLUNFx  I2S Transmit Left x or TDM Channel 2x Underrun (Cleared on read)

ValueDescription
0

Cleared when I2SMCC_ISRA is read.

1

Set when an underrun error occurs in either I2SMCC_THR or I2SMCC_THLxR.

Bits 1, 3, 5, 7 – TXRRDYx  I2S Transmit Right x or TDM Channel [2x]+1 Ready Flag (Cleared by writing I2SMCC_THR/THRxR)

ValueDescription
0

Cleared when a predefined number of write accesses is performed in either I2SMCC_THRxR or I2SMCC_THR. The predefined number depends on the configuration of I2SMCC_MRA.WIRECFG/FORMAT and varies from 1 to 8.

1

Set when I2SMCC_THR or I2SMCC_THRxR is empty.

Bits 0, 2, 4, 6 – TXLRDYx  I2S Transmit Left x or TDM Channel 2x Ready Flag (Cleared by writing I2SMCC_THR/THLxR)

ValueDescription
0

Cleared when a predefined number of write accesses is performed in either I2SMCC_THLxR or I2SMCC_THR. The predefined number depends on the configuration of I2SMCC_MRA.WIRECFG/FORMAT and varies from 1 to 7.

1

Set when I2SMCC_THR or I2SMCC_THLxR is empty.