45.7.16 I2SMCC Receiver Holding Right x Register
| Name: | I2SMCC_RHRxR |
| Offset: | 0x44 + x*0x08 [x=0..3] |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| RHR[31:24] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| RHR[23:16] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RHR[15:8] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RHR[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:0 – RHR[31:0] Receiver Holding Right
Set by hardware to either the last received data word of the right channel on wire x in I2S mode (I2SMCC_MRA.FORMAT = ‘0’) or to the last received data word of the xth +1 TDM channel multiplied by 2. If I2SMCC_MRA.DATALENGTH specifies fewer than 32 bits, data is right-justified in the RHR field.