45.7.13 I2SMCC Receiver Holding Register

Name: I2SMCC_RHR
Offset: 0x30
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
 RHR[31:24] 
Access RRRRRRRR 
Reset 00000000 
Bit 2322212019181716 
 RHR[23:16] 
Access RRRRRRRR 
Reset 00000000 
Bit 15141312111098 
 RHR[15:8] 
Access RRRRRRRR 
Reset 00000000 
Bit 76543210 
 RHR[7:0] 
Access RRRRRRRR 
Reset 00000000 

Bits 31:0 – RHR[31:0] Receiver Holding Register

Set by hardware to the last received data word. If I2SMCC_MRA.DATALENGTH specifies fewer than 32 bits, data is right justified in the RHR field.