45.7.12 I2SMCC Interrupt Status Register B
When I2SMCC_MRB.FIFOEN = 0, TXFFRDY, TXFFEMP, RXFFRDY and RXFFFUL are not relevant. See I2SMCC_ISRA.
| Name: | I2SMCC_ISRB |
| Offset: | 0x2C |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RXFFFUL | RXFFRDY | TXFFEMP | TXFFRDY | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WERR | |||||||||
| Access | R | ||||||||
| Reset | 0 |
Bit 13 – RXFFFUL RX FIFO Full Flag (Cleared on read)
| Value | Description |
|---|---|
| 0 |
Cleared when I2SMCC_ISRB is read. |
| 1 | Set when RX FIFO is full and I2SMCC_MRB.FIFOEN = 1. |
Bit 12 – RXFFRDY RX FIFO Ready Flag (Cleared on read)
| Value | Description |
|---|---|
| 0 |
Cleared when I2SMCC_ISRB is read. |
| 1 | Set when RX FIFO is ready to be read and I2SMCC_MRB.FIFOEN = 1. |
Bit 9 – TXFFEMP TX FIFO Empty Flag (Cleared on read)
| Value | Description |
|---|---|
| 0 |
Cleared when I2SMCC_ISRB is read. |
| 1 | Set when TX FIFO is empty and I2SMCC_MRB.FIFOEN = 1. |
Bit 8 – TXFFRDY TX FIFO Ready Flag (Cleared on read)
| Value | Description |
|---|---|
| 0 |
Cleared when I2SMCC_ISRB is read. |
| 1 | Set when TX FIFO is ready to be written and I2SMCC_MRB.FIFOEN = 1. |
Bit 0 – WERR Write Error Flag (Cleared on read)
| Value | Description |
|---|---|
| 0 | Cleared when the I2SMCC_ISRB is read. |
| 1 | Set when a write occurs in a protected register. |