45.7.11 I2SMCC Interrupt Mask Register B
The following configuration values are valid for the listed bits of this
register:
0: The corresponding source of interrupt is disabled.
1: The corresponding source of interrupt is enabled.
Name: | I2SMCC_IMRB |
Offset: | 0x28 |
Reset: | 0x00000000 |
Property: | Read-only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | | | |
Access | | | | | | | | | |
Reset | | | | | | | | | |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | | | | |
Access | | | | | | | | | |
Reset | | | | | | | | | |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | RXFFFUL | RXFFRDY | | | TXFFEMP | TXFFRDY | |
Access | | | R | R | | | R | R | |
Reset | | | 0 | 0 | | | 0 | 0 | |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | | WERR | |
Access | | | | | | | | R | |
Reset | | | | | | | | 0 | |
Bit 13 – RXFFFUL RX FIFO Full
Interrupt Mask
Bit 12 – RXFFRDY RX FIFO Ready
Interrupt Mask
Bit 9 – TXFFEMP TX FIFO Empty
Interrupt Mask
Bit 8 – TXFFRDY TX FIFO Ready
Interrupt Mask
Bit 0 – WERR Write Error Interrupt
Mask