45.7.11 I2SMCC Interrupt Mask Register B

The following configuration values are valid for the listed bits of this register:

0: The corresponding source of interrupt is disabled.

1: The corresponding source of interrupt is enabled.

Name: I2SMCC_IMRB
Offset: 0x28
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
   RXFFFULRXFFRDY  TXFFEMPTXFFRDY 
Access RRRR 
Reset 0000 
Bit 76543210 
        WERR 
Access R 
Reset 0 

Bit 13 – RXFFFUL RX FIFO Full Interrupt Mask

Bit 12 – RXFFRDY RX FIFO Ready Interrupt Mask

Bit 9 – TXFFEMP TX FIFO Empty Interrupt Mask

Bit 8 – TXFFRDY TX FIFO Ready Interrupt Mask

Bit 0 – WERR Write Error Interrupt Mask