45.7.10 I2SMCC Interrupt Disable Register B
This register can only be written if WPITEN is cleared in the Inter-IC Sound
Write Protection Mode Register.
The following configuration values are valid for the listed bits of this
register:
0: No effect.
1: Disables the corresponding interrupt.
| Name: | I2SMCC_IDRB |
| Offset: | 0x24 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | RXFFFUL | RXFFRDY | | | TXFFEMP | TXFFRDY | |
| Access | | | W | W | | | W | W | |
| Reset | | | – | – | | | – | – | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | | | WERR | |
| Access | | | | | | | | W | |
| Reset | | | | | | | | – | |
Bit 13 – RXFFFUL RX FIFO Full
Interrupt Disable
Bit 12 – RXFFRDY RX FIFO Ready
Interrupt Disable
Bit 9 – TXFFEMP TX FIFO Empty
Interrupt Disable
Bit 8 – TXFFRDY TX FIFO Ready
Interrupt Disable
Bit 0 – WERR Write Error Interrupt
Disable
