45.7.14 I2SMCC Transmitter Holding Register

Name: I2SMCC_THR
Offset: 0x34
Reset: 
Property: Write-only

Bit 3130292827262524 
 THR[31:24] 
Access WWWWWWWW 
Reset  
Bit 2322212019181716 
 THR[23:16] 
Access WWWWWWWW 
Reset  
Bit 15141312111098 
 THR[15:8] 
Access WWWWWWWW 
Reset  
Bit 76543210 
 THR[7:0] 
Access WWWWWWWW 
Reset  

Bits 31:0 – THR[31:0] Transmitter Holding Register

Next data word to be transmitted after the current word if TXLRDYx or TXRRDYx is not set. If I2SMCC_MRA.DATALENGTH specifies fewer than 32 bits, data is right-justified in the THR field.