17.5.8.1 Refresh Using Direct Software Request of Refresh Command

Follow these steps to put the UDDRC in direct software request of Refresh Command mode:

1. Set the RFSHCTL3.dis_auto_refresh bit to 1. When the register bit is set, the UDDRC checks for any pending refreshes. Any pending refreshes are issued right away using the ‘critical refresh’ feature inside the UDDRC. After these refreshes are issued, all the refresh timers inside the UDDRC are reset to 0. They are re-activated only when the auto-refresh feature is enabled.
2. The SoC core must keep track of the refresh requirements of the SDRAM.
3. The refresh command can be issued by setting the register bits DBGCMD.rank*_refresh to 1 (see Register Descriptions). When the rank*_refresh request is stored in the UDDRC, the corresponding register bit is automatically cleared. The SoC core can initiate a rank*_refresh operation only if DBGSTAT.rank*_refresh_busy is low. The UDDRC issues refresh to the SDRAM at the earliest.
4. Software-driven refresh commands for each rank are loaded into a 9-entry buffer, and are issued by the UDDRC on the DFI as soon as it is legal to do so (the UDDRC controller must wait t_RFC(min) between each refresh request). If the buffer saturates, the DBGSTAT.rank*_refresh_busy remains asserted to prevent software from initiating further refreshes.