30.6.1 OTPC Control Register

This register can only be written if the WPCTEN bit is cleared in the OTPC Write Protection Mode Register.

Name: OTPC_CR
Offset: 0x00
Reset: 
Property: Write-only

Bit 3130292827262524 
 KEY[15:8] 
Access WWWWWWWW 
Reset  
Bit 2322212019181716 
 KEY[7:0] 
Access WWWWWWWW 
Reset  
Bit 15141312111098 
 REFRESH     KBSTOPKBSTART 
Access WWW 
Reset  
Bit 76543210 
 FLUSHREAD HIDE INVLDCKSGENPGM 
Access WWWWWW 
Reset  

Bits 31:16 – KEY[15:0] Programming Key

This field must be written with the correct key code (0x7167) to allow programming, checksum generation, packet invalidation or packet hiding.

Bit 15 – REFRESH Refresh the Area

ValueDescription
0 No effect.
1 Starts a refresh of the area.

Bit 9 – KBSTOP Key Bus Transfer Stop

ValueDescription
0 No effect.
1 Stops an on-going transfer on the host key bus.

Bit 8 – KBSTART Key Bus Transfer Start

ValueDescription
0 No effect.
1 Starts a transfer through the host key bus.

Bit 7 – FLUSH Flush Temporary Registers

ValueDescription
0 No effect.
1 Starts a flush of the temporary registers used to store the packet payload.

Bit 6 – READ Read Packet

ValueDescription
0 No effect.
1 Starts a read sequence of the selected packet.

Bit 4 – HIDE Hide Packet

ValueDescription
0 No effect.
1 The selected packet is not readable anymore until the next reset.

Bit 2 – INVLD Invalidate Packet

ValueDescription
0 No effect.
1 Invalidates the selected packet.

Bit 1 – CKSGEN Generate Checksum

ValueDescription
0 No effect.
1 Generates and programs the selected packet checksum. This action also locks the packet.

Bit 0 – PGM Program Packet

ValueDescription
0 No effect.
1 The selected packet is written.