30.6.7 OTPC Interrupt Mask Register
The following configuration values are valid for all listed bit names of this register:
0: Corresponding interrupt is not enabled.
1: Corresponding interrupt is enabled.
| Name: | OTPC_IMR |
| Offset: | 0x18 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | SECE | | | | | |
| Access | | | | R | | | | | |
| Reset | | | | 0 | | | | | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | | | | KBERR | |
| Access | | | | | | | | R | |
| Reset | | | | | | | | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | HDERR | COERR | CKERR | EORF | EOH | EOF | EOR | |
| Access | | R | R | R | R | R | R | R | |
| Reset | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | WERR | IVERR | LKERR | PGERR | EOKT | EOI | EOL | EOP | |
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 28 – SECE Security and/or Safety Event Interrupt Mask
Bit 16 – KBERR Key Bus Error Interrupt Mask
Bit 14 – HDERR Hide Error Interrupt Mask
Bit 13 – COERR Corruption Error Interrupt Mask
Bit 12 – CKERR Checksum Check Error Interrupt Mask
Bit 11 – EORF End Of Refresh Interrupt Mask
Bit 10 – EOH End Of Hide Interrupt Mask
Bit 9 – EOF End Of Flush Interrupt Mask
Bit 8 – EOR End Of Read Interrupt Mask
Bit 7 – WERR Write Error Interrupt Mask
Bit 6 – IVERR Invalidation Error Interrupt Mask
Bit 5 – LKERR Locking Error Interrupt Mask
Bit 4 – PGERR Programming Error Interrupt Mask
Bit 3 – EOKT End Of Key Transfer Interrupt Mask
Bit 2 – EOI End Of Invalidation Interrupt Mask
Bit 1 – EOL End Of Locking Interrupt Mask
Bit 0 – EOP End Of Programming Interrupt Mask
