30.6.2 OTPC Mode Register

This register can only be written if the WPCFEN bit is cleared in the OTPC Write Protection Mode Register.

Name: OTPC_MR
Offset: 0x04
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
 ADDR[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 ADDR[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 LOCK KBDST[1:0]  WRDISRDDIS 
Access R/WR/WR/WR/WR/W 
Reset 00000 
Bit 76543210 
 EMUL  NPCKT   UHCRRDIS 
Access R/WR/WR/W 
Reset 000 

Bits 31:16 – ADDR[15:0] Address

This field represents the address of the packet’s header.

Bit 15 – LOCK Lock Register

The LOCK bit is set-only. Only a reset can disable lock.
ValueDescription
0 The OTPC_MR register is unlocked; write access changes its value.
1 The OTPC_MR register is locked; write access does not change its value.

Bits 13:12 – KBDST[1:0] Key Bus Destination

ValueNameDescription
0 NONE No destination selected (no transfer can occur).
1 AES The AES is the destination of the key transfer.
2 TZAESB The TrustZone AES Bridge is the destination of the key transfer.
3 TDES The TDES is the destination of the key transfer.

Bit 9 – WRDIS Write Disable

ValueDescription
0 The write capability of the OTPC_DR register is enabled.
1 The write capability of the OTPC_DR register is disabled.

Bit 8 – RDDIS Read Disable

ValueDescription
0 The read capability of the OTPC_HR and OTPC_DR registers are enabled.
1 The read capability of the OTPC_HR and OTPC_DR registers are disabled. In case of read, the returned value is 0.

Bit 7 – EMUL Emulation Enable

ValueDescription
0 The Emulation mode of the User area is disabled, all accesses are computed in the OTP memory.
1 The Emulation mode of the User area is enabled, all accesses are computed in the Emulation memory.

Bit 4 – NPCKT New Packet

ValueDescription
0 Updates the packet defined at the ADDR address.
1 Creates a new packet.

Bit 0 – UHCRRDIS User Hardware Configuration Register Read Disable

ValueDescription
0 The User Hardware Configuration register can be read through the User Interface.
1 The User Hardware Configuration register cannot be read through the User Interface.