30.6.18 OTPC Write Protection Status Register
| Name: | OTPC_WPSR |
| Offset: | 0xE8 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| ECLASS | SWETYP[3:0] | ||||||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| WPVSRC[15:8] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WPVSRC[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SWE | SEQE | CGD | WPVS | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 31 – ECLASS Software Error Class
| Value | Name | Description |
|---|---|---|
| 0 | WARNING | An abnormal access that does not have any impact. |
| 1 | ERROR | An abnormal access that may have an impact. |
Bits 27:24 – SWETYP[3:0] Software Error Type
| Value | Name | Description |
|---|---|---|
| 0 | READ_WO | A write-only register has been read (warning). |
| 1 | WRITE_RO | A write access has been performed on a read-only register (warning). |
| 2 | CONF_CHG | A change has been made into the configuration (error). |
| 3 | KEY_ERROR | A write has been computed in OTPC_CR or OTPC_WPMR register with a wrong value in the related KEY field (error). |
| 4 | DATA_ACC | The non-secure world application tried to read a packet from the secure world (error). |
Bits 23:8 – WPVSRC[15:0] Write Protection Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
Bit 3 – SWE Software Control Error (cleared on read)
| Value | Description |
|---|---|
| 0 | No software error has occurred since the last read of OTPC_WPSR. |
| 1 | A software error has occurred since the last read of OTPC_WPSR. The field SWETYP details the type of software error encountered. |
Bit 2 – SEQE Internal Sequencer Error (cleared on read)
| Value | Description |
|---|---|
| 0 | No peripheral internal sequencer error has occurred since the last read of OTPC_WPSR. |
| 1 | A peripheral internal sequencer error has occurred since the last read of OTPC_WPSR. This flag can be set under abnormal operating conditions. |
Bit 1 – CGD Clock Glitch Detected (cleared on read)
| Value | Description |
|---|---|
| 0 | No clock glitch has occurred since the last read of OTPC_WPSR. |
| 1 | A clock glitch has occurred since the last read of OTPC_WPSR. This flag can be set under abnormal operating conditions. |
Bit 0 – WPVS Write Protection Violation Status (cleared on read)
| Value | Description |
|---|---|
| 0 | No write protection violation has occurred since the last read of OTPC_WPSR. |
| 1 | A write protection violation has occurred since the last read of OTPC_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into WPVSRC. |