30.6.5 OTPC Interrupt Enable Register
This register can only be written if the WPITEN bit is cleared in the OTPC Write Protection Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
| Name: | OTPC_IER |
| Offset: | 0x10 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | SECE | | | | | |
| Access | | | | W | | | | | |
| Reset | | | | – | | | | | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | | | | KBERR | |
| Access | | | | | | | | W | |
| Reset | | | | | | | | – | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | HDERR | COERR | CKERR | EORF | EOH | EOF | EOR | |
| Access | | W | W | W | W | W | W | W | |
| Reset | | – | – | – | – | – | – | – | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | WERR | IVERR | LKERR | PGERR | EOKT | EOI | EOL | EOP | |
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – | |
Bit 28 – SECE Security and/or Safety Event Interrupt Enable
Bit 16 – KBERR Key Bus Error Interrupt Enable
Bit 14 – HDERR Hide Error Interrupt Enable
Bit 13 – COERR Corruption Error Interrupt Enable
Bit 12 – CKERR Checksum Check Error Interrupt Enable
Bit 11 – EORF End Of Refresh Interrupt Enable
Bit 10 – EOH End Of Hide Interrupt Enable
Bit 9 – EOF End Of Flush Interrupt Enable
Bit 8 – EOR End Of Read Interrupt Enable
Bit 7 – WERR Write Error Interrupt Enable
Bit 6 – IVERR Invalidation Error Interrupt Enable
Bit 5 – LKERR Locking Error Interrupt Enable
Bit 4 – PGERR Programming Error Interrupt Enable
Bit 3 – EOKT End Of Key Transfer Interrupt Enable
Bit 2 – EOI End Of Invalidation Interrupt Enable
Bit 1 – EOL End Of Locking Interrupt Enable
Bit 0 – EOP End Of Programming Interrupt Enable
