17.5.1.4 Software Coherency for AXI Ports

The Address Collision Handling section describes how the DDRC handles in-order execution of commands to the same address.

For the commands issued at the AXI port, the logic in the DDRC protects against all types of software coherency hazards when the AXI host waits for write (read) response before sending the next same address read (same address write) or vice-versa.