17.5.5.2 VPR/VPW Timeout

There are separate timeouts for the blue and red queues for read transactions, and one timeout for write transactions. Timers are started to down count when the transaction is accepted in the XPI, which are then forwarded to DDRC together with the command.

Timeouts are set per port and queue using PCFGQOS1_n and PCFGWQOS1_n registers (see UDDRC_PCFGQOS1_0 and UDDRC_PCFGWQOS1_0).

For PCFGQOS1_n register:

• RQOS_MAP_TIMEOUTB: specifies the timeout value for transactions mapped to the blue queue.
• RQOS_MAP_TIMEOUTR: specifies the timeout value for transactions mapped to the red queue.

For PCFGWQOS1_n register:

• WQOS_MAP_TIMEOUT: specifies the timeout value for write transactions.

When expired, VPR/VPW transactions from XPI are tagged as expired-VPR or expired-VPW instead of LPR/NPW during normal priority transaction flow. The Port Arbiter treats these transactions with the highest priority (priority0). In addition, the Port Arbiter asserts hif_go2critical_lpr signal to the DDRC if there are no LPR credits available (LPR store of the read CAM is full) when an expired-VPR port is pending, and hif_go2critical_wr signal to the DDRC if there are no write credits available when an expired-VPW is pending. If an expired-VPW is issued as RMW at the HIF interface, the Port Arbiter asserts hif_go2critical_lpr signal to the DDRC if there are no LPR credits hif_go2critical_lpr and hif_go2critical_wr are asserted at the same time, priority in the DDRC is given to the read.

If VPR/VPW timeout registers are set to 0, the VPR/VPW transactions expire immediately as they enter the DDRMC, thereby making them the highest priority transaction class within the device. If multiple VPR/VPW transactions expire at the same time in the XPI, they are executed by the PA in round-robin order.