17.80 UDDRC AXI Port 0 Read QoS Configuration Register 1
| Name: | UDDRC_PCFGQOS1_0 |
| Offset: | 0x498 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| RQOS_MAP_TIMEOUTR[10:8] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| RQOS_MAP_TIMEOUTR[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RQOS_MAP_TIMEOUTB[10:8] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RQOS_MAP_TIMEOUTB[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 26:16 – RQOS_MAP_TIMEOUTR[10:0]
Specifies the timeout value for transactions mapped to the red address queue.
Programming Mode: Quasi-dynamic Group 3
Bits 10:0 – RQOS_MAP_TIMEOUTB[10:0]
Specifies the timeout value for transactions mapped to the blue address queue.
Programming Mode: Quasi-dynamic Group 3