3.4.3.3.2 Cached Data Error

The second method of PBU error handling occurs when the cache has detected a parity error on a cached line of program word data. When valid program data is cached for later consumption, then the error status bit is stripped, and the program data word is stored in the cache memory. A single even parity bit is calculated and stored along with the data. This parity bit is used to protect the system from data corruption that could occur in the cache RAM.

A maskable interrupt event is generated by the PBU when a parity error is detected on a cache line. In this case, the cache will invalidate the line with the parity error and the program data must be re-fetched from the program memory. Other than the interrupt event, the only other effect that can be observed during a cache parity error is additional execution latency caused by Flash program fetch. No address associated with the parity error is captured.