25.4.3.3 Logic Function

Logic functions are shown in Figure 25-3. Each logic function has four inputs and one output. The MODE[2:0] bits (CLCxCON[2:0]) set the functional behavior of the logic cell. There are four combinatorial options and four state options. Three of the state options define Input Gate 1 as a rising edge clock with the traditional meanings of D and J-K flip-flops. The fourth state option, MODE[2:0] bits = 111, is a transparent latch; Q follows D when Latch Enable (LE) is true; Q holds state when LE is false. For options with both S (Set) and R (Reset) inputs, the output changes asynchronously to the clock when S or R is a logic ‘1’; R is dominant.