25.4.2 CLC Setup

CLCxCON selects the logic function and determines and controls the I/O pins. This register also controls output signal polarity. The ON bit (CLCxCON[15]) must be set for the CLC to operate. All registers can be programmed while ON is clear.

The CLCxSEL (CLCxSEL) register controls which input signals are routed to the input bus of Figure 25-2. Both the True (T) and Negated (N) values are made available in the data bus.

The CLCxGLS (CLCxGLS) register selects which signals from the data bus are applied to the input OR gates. True and Negated inputs are separately enabled; do not enable both for the same signal.

The final polarity of the CLC module output is controlled by the LCPOL bit (CLCxCON[5]). The output is inverted when LCPOL = 1 and uninverted when LCPOL = 0. The GxPOL bits (CLCxCON[19:16]) control the polarity of the logic function inputs.

The INTP and INTN bits (CLCxCON[11:10]) enable interrupts on the rising and falling edge of the CLC output.

The LCOUT bit is read-only and reflects the status of the logic cell output. To output the CLCxOUT signal to an I/O pin, set the LCOE bit and configure the I/O as a digital output. The CLCxOUT signal is made available through Peripheral Pin Select (PPS) and will need to be configured.