4.4.1.1 Priority Overrides

The BMXINITPR register can be used to temporarily override the default priority scheme when accessing RAM targets. When the corresponding bit is set, an initiator will have its priority raised above the native priorities of the CPU and other initiators. The ICD bus master does not support priority overrides; it will always be the lowest priority and does not have an associated BMXINITPR bit.

If multiple override bits are set, priority between the overridden initiators is determined by their natural priority order. For initiators that do not win arbitration, the BMX will stall the initiator of the lower priority transaction until a subsequent cycle, after the target access completes, when the initiator does win arbitration. Losing initiators will be forced to stall until no higher priority initiators are requesting the target.