3.6.8.1 Floating-Point Unit Registers

The Floating-Point Unit (FPU) provides a large set of working registers (F-regs):

  • 32 x 32-bit (Single Precision, F0 ... F31) or
  • 16 x 64-bit (Double Precision, F0, F2 ... F28, F30) or
  • A mix of the two sizes aligned as shown in Figure 3-21.

In addition to the F-regs, status (FSR) and control (FCR) registers are also supported as shown in Figure 3-21:

  • FSR (FPU Status Register, 32-bit): Holds the status of retired floating-point instructions:
    • FSR [6:0]: Instruction “most-recent” exception status
    • FSR [14:8]: Instruction "sticky" exception status
    • FSR [19:16]: FCPS/FCPQ instruction status
    • FSR [28:24]: FTST instruction status
  • FCR (FPU Control Register, 16-bit):
    • FCR [6:0]: Exception mask control
    • FCR [9:8]: Rounding mode control
    • FCR [10]: Subnormal result “Flush-to-Zero” (FTZ) control
    • FCR [11]: Subnormal operand “Subnormals-are-Zero” (SAZ) control
  • FEAR: (FPU Exception Address Capture Register, 24-bit): Holds the address of the first instruction encountered that causes an exception. All subsequent instructions in the FPU pipeline that subsequently retire will not affect the FEAR, even if they too generate exceptions. The FEAR is intended for use during debug of the floating-point software.
Note: The FSR upper and lower 16 bits (represented as FSRH and FSRL, respectively) may be read/written independently of each other by some instructions.
Note: Although inconsistent with device interrupts, where interrupt controls are referred to as enables (where logic 1 represents enabled), it is more conventional (and in keeping with the IEEE-754 specification) that the FPU exception controls be referred to as masks (where logic 1 represents masked). These bits are all set at Reset, masking exceptions by default.