3.6.8.3 FPU Register Set

The FPU Programmer’s Model of registers is shown in Figure 3-21 and is comprised of floating-point operand registers (F-regs), a floating-point control register (FCR), a floating-point status register (FSR), and a floating-point exception address capture register (FEAR). None of the registers are memory-mapped and must be read or written by the CPU using the coprocessor move instructions (MOVCRW, MOVWCR, PUSHCR, POPCR, LDWLOCR, STWLOCR, and MOVLCR). The FCR, FSR and FEAR registers may also be subjected to a literal AND or OR operation by the FAND and FIOR instructions, respectively.