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25.3.2 Configurable Logic Cell x
Input MUX Select Register
Table 25-7. Register Bit Attribute Legend Symbol Description Symbol Description Symbol Description R Readable
bit HC Cleared by
Hardware (Gray
cell) Unimplemented W Writable
bit HS Set by
Hardware X Bit is unknown
at Reset C Write to
clear S Software
settable bit x Channel
number
Name: CLCxSEL Offset: 0x3A64, 0x3A74,
0x3A84, 0x3A94
Bit 31 30 29 28 27 26 25 24 Access Reset
Bit 23 22 21 20 19 18 17 16 Access Reset
Bit 15 14 13 12 11 10 9 8 DS4[2:0] DS3[2:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0 DS2[2:0] DS1[2:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0
Bits 14:12 – DS4[2:0] Data Selection MUX
4 Signal Selection bits (Main) Bits 10:8 – DS3[2:0] Data Selection MUX
3 Signal Selection bits (Main) Bits 6:4 – DS2[2:0] Data Selection MUX
2 Signal Selection bits (Main) Bits 2:0 – DS1[2:0] Data Selection MUX
1 Signal Selection bits (Main)
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