25.3.1 Configurable Logic Cell x Control Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | CLCxCON |
| Offset: | 0x3A60, 0x3A70, 0x3A80, 0x3A90 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| G4POL | G3POL | G2POL | G1POL | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ON | INTP | INTN | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LCOE | LCOUT | LCPOL | MODE[2:0] | ||||||
| Access | R/W | R | R | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bit 19 – G4POL Gate 4 Polarity Control bit
| Value | Description |
|---|---|
1 | The output of Gate 4 logic is inverted when applied to the logic cell |
0 | The output of Gate 4 logic is not inverted |
Bit 18 – G3POL Gate 3 Polarity Control bit
| Value | Description |
|---|---|
1 | The output of Gate 3 logic is inverted when applied to the logic cell |
0 | The output of Gate 3 logic is not inverted |
Bit 17 – G2POL Gate 2 Polarity Control bit
| Value | Description |
|---|---|
1 | The output of Gate 2 logic is inverted when applied to the logic cell |
0 | The output of Gate 2 logic is not inverted |
Bit 16 – G1POL Gate 1 Polarity Control bit
| Value | Description |
|---|---|
1 | The output of Gate 1 logic is inverted when applied to the logic cell |
0 | The output of Gate 1 logic is not inverted |
Bit 15 – ON Configurable Logic Cell Enable bit
| Value | Description |
|---|---|
1 | Configurable Logic Cell is enabled and mixing input signals |
0 | Configurable Logic Cell is disabled and has logic zero outputs |
Bit 11 – INTP Configurable Logic Cell Positive Edge Interrupt Enable bit
| Value | Description |
|---|---|
1 | Interrupt will be generated when a rising edge occurs on LCOUT |
0 | Interrupt will not be generated |
Bit 10 – INTN Configurable Logic Cell Negative Edge Interrupt Enable bit
| Value | Description |
|---|---|
1 | Interrupt will be generated when a falling edge occurs on LCOUT |
0 | Interrupt will not be generated |
Bit 7 – LCOE Configurable Logic Cell Port Enable bit
| Value | Description |
|---|---|
1 | Configurable Logic Cell port pin output is enabled |
0 | Configurable Logic Cell port pin output is disabled |
Bit 6 – LCOUT Configurable Logic Cell Data Output Status bit
| Value | Description |
|---|---|
1 | Configurable Logic Cell output high |
0 | Configurable Logic Cell output low |
Bit 5 – LCPOL Configurable Logic Cell Output Polarity Control bit
| Value | Description |
|---|---|
1 | The output of the module is inverted |
0 | The output of the module is not inverted |
Bits 2:0 – MODE[2:0] Configurable Logic Cell Mode bits
| Value | Description |
|---|---|
111 | Cell is one-input transparent latch with S and R |
110 | Cell is J-K flip-flop with R |
101 | Cell is two-input D flip-flop with R |
100 | Cell is one-input D flip-flop with S and R |
011 | Cell is SR latch |
010 | Cell is four-input AND |
001 | Cell is OR-XOR |
000 | Cell is AND-OR |