25.3.3 Configurable Logic Cell x Source Enable Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | CLCxGLS |
| Offset: | 0x3A68, 0x3A78, 0x3A88, 0x3A98 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| G4D4T | G4D4N | G4D3T | G4D3N | G4D2T | G4D2N | G4D1T | G4D1N | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| G3D4T | G3D4N | G3D3T | G3D3N | G3D2T | G3D2N | G3D1T | G3D1N | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| G2D4T | G2D4N | G2D3T | G2D3N | G2D2T | G2D2N | G2D1T | G2D1N | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| G1D4T | G1D4N | G1D3T | G1D3N | G1D2T | G1D2N | G1D1T | G1D1N | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 31 – G4D4T Gate 4 Data 4 True Enable bit
| Value | Description |
|---|---|
1 | The Data 4 (noninverted) signal is enabled for Gate 4 |
0 | The Data 4 (noninverted) signal is disabled for Gate 4 |
Bit 30 – G4D4N Gate 4 Data 4 Negated Enable bit
| Value | Description |
|---|---|
1 | The Data 4 (inverted) signal is enabled for Gate 4 |
0 | The Data 4 (inverted) signal is disabled for Gate 4 |
Bit 29 – G4D3T Gate 4 Data 3 True Enable bit
| Value | Description |
|---|---|
1 | The Data 3 (noninverted) signal is enabled for Gate 4 |
0 | The Data 3 (noninverted) signal is disabled for Gate 4 |
Bit 28 – G4D3N Gate 4 Data 3 Negated Enable bit
| Value | Description |
|---|---|
1 | The Data 3 (inverted) signal is enabled for Gate 4 |
0 | The Data 3 (inverted) signal is disabled for Gate 4 |
Bit 27 – G4D2T Gate 4 Data 2 True Enable bit
| Value | Description |
|---|---|
1 | The Data 2 (noninverted) signal is enabled for Gate 4 |
0 | The Data 2 (noninverted) signal is disabled for Gate 4 |
Bit 26 – G4D2N Gate 4 Data 2 Negated Enable bit
| Value | Description |
|---|---|
1 | The Data 2 (inverted) signal is enabled for Gate 4 |
0 | The Data 2 (inverted) signal is disabled for Gate 4 |
Bit 25 – G4D1T Gate 4 Data 1 True Enable bit
| Value | Description |
|---|---|
1 | The Data 1 (noninverted) signal is enabled for Gate 4 |
0 | The Data 1 (noninverted) signal is disabled for Gate 4 |
Bit 24 – G4D1N Gate 4 Data 1 Negated Enable bit
| Value | Description |
|---|---|
1 | The Data 1 (inverted) signal is enabled for Gate 4 |
0 | The Data 1 (inverted) signal is disabled for Gate 4 |
Bit 23 – G3D4T Gate 3 Data 4 True Enable bit
| Value | Description |
|---|---|
1 | The Data 4 (noninverted) signal is enabled for Gate 3 |
0 | The Data 4 (noninverted) signal is disabled for Gate 3 |
Bit 22 – G3D4N Gate 3 Data 4 Negated Enable bit
| Value | Description |
|---|---|
1 | The Data 4 (inverted) signal is enabled for Gate 3 |
0 | The Data 4 (inverted) signal is disabled for Gate 3 |
Bit 21 – G3D3T Gate 3 Data 3 True Enable bit
| Value | Description |
|---|---|
1 | The Data 3 (noninverted) signal is enabled for Gate 3 |
0 | The Data 3 (noninverted) signal is disabled for Gate 3 |
Bit 20 – G3D3N Gate 3 Data 3 Negated Enable bit
| Value | Description |
|---|---|
1 | The Data 3 (inverted) signal is enabled for Gate 3 |
0 | The Data 3 (inverted) signal is disabled for Gate 3 |
Bit 19 – G3D2T Gate 3 Data 2 True Enable bit
| Value | Description |
|---|---|
1 | The Data 2 (noninverted) signal is enabled for Gate 3 |
0 | The Data 2 (noninverted) signal is disabled for Gate 3 |
Bit 18 – G3D2N Gate 3 Data 2 Negated Enable bit
| Value | Description |
|---|---|
1 | The Data 2 (inverted) signal is enabled for Gate 3 |
0 | The Data 2 (inverted) signal is disabled for Gate 3 |
Bit 17 – G3D1T Gate 3 Data 1 True Enable bit
| Value | Description |
|---|---|
1 | The Data 1 (noninverted) signal is enabled for Gate 3 |
0 | The Data 1 (noninverted) signal is disabled for Gate 3 |
Bit 16 – G3D1N Gate 3 Data 1 Negated Enable bit
| Value | Description |
|---|---|
1 | The Data 1 (inverted) signal is enabled for Gate 3 |
0 | The Data 1 (inverted) signal is disabled for Gate 3 |
Bit 15 – G2D4T Gate 2 Data 4 True Enable bit
| Value | Description |
|---|---|
1 | The Data 4 (noninverted) signal is enabled for Gate 2 |
0 | The Data 4 (noninverted) signal is disabled for Gate 2 |
Bit 14 – G2D4N Gate 2 Data 4 Negated Enable bit
| Value | Description |
|---|---|
1 | The Data 4 (inverted) signal is enabled for Gate 2 |
0 | The Data 4 (inverted) signal is disabled for Gate 2 |
Bit 13 – G2D3T Gate 2 Data 3 True Enable bit
| Value | Description |
|---|---|
1 | The Data 3 (noninverted) signal is enabled for Gate 2 |
0 | The Data 3 (noninverted) signal is disabled for Gate 2 |
Bit 12 – G2D3N Gate 2 Data 3 Negated Enable bit
| Value | Description |
|---|---|
1 | The Data 3 (inverted) signal is enabled for Gate 2 |
0 | The Data 3 (inverted) signal is disabled for Gate 2 |
Bit 11 – G2D2T Gate 2 Data 2 True Enable bit
| Value | Description |
|---|---|
1 | The Data 2 (noninverted) signal is enabled for Gate 2 |
0 | The Data 2 (noninverted) signal is disabled for Gate 2 |
Bit 10 – G2D2N Gate 2 Data 2 Negated Enable bit
| Value | Description |
|---|---|
1 | The Data 2 (inverted) signal is enabled for Gate 2 |
0 | The Data 2 (inverted) signal is disabled for Gate 2 |
Bit 9 – G2D1T Gate 2 Data 1 True Enable bit
| Value | Description |
|---|---|
1 | The Data 1 (noninverted) signal is enabled for Gate 2 |
0 | The Data 1 (noninverted) signal is disabled for Gate 2 |
Bit 8 – G2D1N Gate 2 Data 1 Negated Enable bit
| Value | Description |
|---|---|
1 | The Data 1 (inverted) signal is enabled for Gate 2 |
0 | The Data 1 (inverted) signal is disabled for Gate 2 |
Bit 7 – G1D4T Gate 1 Data 4 True Enable bit
| Value | Description |
|---|---|
1 | The Data 4 (noninverted) signal is enabled for Gate 1 |
0 | The Data 4 (noninverted) signal is disabled for Gate 1 |
Bit 6 – G1D4N Gate 1 Data 4 Negated Enable bit
| Value | Description |
|---|---|
1 | The Data 4 (inverted) signal is enabled for Gate 1 |
0 | The Data 4 (inverted) signal is disabled for Gate 1 |
Bit 5 – G1D3T Gate 1 Data 3 True Enable bit
| Value | Description |
|---|---|
1 | The Data 3 (noninverted) signal is enabled for Gate 1 |
0 | The Data 3 (noninverted) signal is disabled for Gate 1 |
Bit 4 – G1D3N Gate 1 Data 3 Negated Enable bit
| Value | Description |
|---|---|
1 | The Data 3 (inverted) signal is enabled for Gate 1 |
0 | The Data 3 (inverted) signal is disabled for Gate 1 |
Bit 3 – G1D2T Gate 1 Data 2 True Enable bit
| Value | Description |
|---|---|
1 | The Data 2 (noninverted) signal is enabled for Gate 1 |
0 | The Data 2 (noninverted) signal is disabled for Gate 1 |
Bit 2 – G1D2N Gate 1 Data 2 Negated Enable bit
| Value | Description |
|---|---|
1 | The Data 2 (inverted) signal is enabled for Gate 1 |
0 | The Data 2 (inverted) signal is disabled for Gate 1 |
Bit 1 – G1D1T Gate 1 Data 1 True Enable bit
| Value | Description |
|---|---|
1 | The Data 1 (noninverted) signal is enabled for Gate 1 |
0 | The Data 1 (noninverted) signal is disabled for Gate 1 |
Bit 0 – G1D1N Gate 1 Data 1 Negated Enable bit
| Value | Description |
|---|---|
1 | The Data 1 (inverted) signal is enabled for Gate 1 |
0 | The Data 1 (inverted) signal is disabled for Gate 1 |