3.6.8.3.4 Intra-FPU Register Moves and Logical Operations

In addition to CPU to/from FPU data movement, the FPU supports instructions that execute within its own pipeline that perform register to register moves or logical operations:

FMOV: Copy any F-reg or F-reg pair into another F-reg or F-reg pair.
FMOVC: Move one of 32 Single or Double Precision constant values into an F-reg or F-reg pair.
FAND: Logically AND a 16-bit literal value (lit16) with the lsw of the FPU FSR, FCR or FEAR.
FIOR: Logically OR a 16-bit literal value (lit16) with the lsw of the FPU FSR, FCR or FEAR.

Note: To allow subsequent instruction to immediately utilize FAND and FIOR changes to FCR.RND[1:0] and FCR.SAZ control bits without stalls, these bits are manipulated and updated in the first pipeline stage (RD-stage). However, the remaining FCR bits are not written back until the end of the instruction as usual. Consequently, should the CPU need to read the FCR immediately after modification, it will be stalled by the FPU until the FAND or FIOR instruction has retired.