20.5.2.6 Generating a Repeated Start Bus Event

Setting the RSEN bit (I2CxCON1[1]) enables the generation of a host repeated start sequence, as illustrated in Figure 20-13.

Note: The lower five bits of the I2CxCON1 register must be ‘0’ (host logic inactive) before attempting to set the RSEN bit.

To generate a Repeated Start condition, the user software sets the RSEN bit. The host module asserts the SCLx pin low. When the module samples the SCLx pin low, the module releases the SDAx pin for 1 TBRG. When the BRG times out and the module samples SDAx high, the module deasserts the SCLx pin. When the module samples the SCLx pin high, the BRG reloads and begins counting. SDAx and SCLx must be sampled high for 1 TBRG. This action is then followed by assertion of the SDAx pin low for 1 TBRG while SCLx is high.

The following is the repeated start sequence:

  1. The client detects the Start condition, sets the S status bit (I2CxSTAT1[3]) and clears the P status bit (I2CxSTAT1[4]).
  2. The RSEN bit is automatically cleared.
  3. The I2C module generates the I2CxIF interrupt if HSCIE(I2CxINTC[27]) bit and HSTIE(I2CxINTC[13]) are enabled.

Figure 20-13. Host Repeated Start Timing Diagram