20.5.2.3 Receiving Data from a Client Device

The host can receive data from the client device after the host has transmitted the client address with a R/W status bit value of ‘1’. After receiving ACK from the client for the address, configure packet size (PSZ,(I2CxCON2[15:0]) and then enable RCEN bit (I2CxCON1[3]) for the first data byte to be received. If SMART mode (SMEN, I2CxCON2 [17]) is enabled, then the hardware will automatically set RCEN(I2CxCON1[3]) based on the status of RBF(I2CxSTAT1[1]) and PSZ (I2CxCON2[15:0]) for remaining bytes; otherwise, the user software should set RCEN(I2CxCON1[3]) for every byte to be received. The host logic begins to generate clocks and before each falling edge of the SCLx, the SDAx line is sampled and data is shifted into the I2CxRSR register.

Note: The lower five bits of the I2CxCON1 register must be ‘0’ before attempting to set the RCEN bit. This ensures that the host logic is inactive.

After the falling edge of the eighth SCLx clock, the following events occur:

  • The RCEN bit is automatically cleared
  • The contents of the I2CxRSR register transfer into the I2CxRCV register
  • The RBF status bit (I2CxSTAT1[1]) is set
  • The I2C module generates the I2CxIF interrupt if HDRXIE (I2CxINTC[0]) bit and HSTIE(I2CxINTC[13]) are enabled

When the CPU reads the receive buffer (I2CxRCV), the RBF status bit is automatically cleared. The user software can process the data and then execute an Acknowledge sequence.

If SMART mode is enabled, the hardware will automatically set RCEN(I2CxCON1[3]) based on the status of RBF(I2CxSTAT1[1]) and PSZ (I2CxCON2[15:0]) for remaining bytes; otherwise the user software should set RCEN(I2CxCON1[3]) for every byte to be received.

If the receive buffer (I2CxRCV) is full and packet size (I2CxCON2[15:0]) has not reached zero, the I2CxSTAT.SSPND bit is set and the host drives SCL low. The user should remove the Receiver Full condition by reading the receive buffer (I2CxRCV). Once the full condition is removed, I2CxSTAT.SSPND will be cleared by hardware. Once packet size becomes zero, end of packet (EOP) will be set (I2CxSTAT2[24]), if enabled (EOPSC, I2CxCON2[20:19]). The sequence of events that occurs during host reception is illustrated in Figure 20-9.

Figure 20-9. Host Reception Timing Diagram