20.5.4.4.3 Wait States During Client Receptions

When the client receives a data byte, the host can potentially begin sending the next byte immediately. This allows the user software controlling the nine client SCLx clock periods to process the previously received byte. If this is not enough time, the client software may want to generate a bus Wait period.

The STREN bit (I2CxCON1[6]) enables a bus Wait to occur on client receptions. When STREN = 1 at the falling edge of the ninth SCLx clock of a received byte, the client clears the SCLREL bit. Clearing the SCLREL bit causes the client to pull the SCLx line low, initiating a Wait. The SCLx clock of the host and client will synchronize, as provided in Host Clock Synchronization.

When the user software is ready to resume reception, the user software sets the SCLREL bit. This causes the client to release the SCLx line and the host resumes clocking. If SMART mode (SMEN, I2CxCON2[17]) is enabled, hardware will automatically release SCL by setting SCLREL when the received byte is read (RBF=0) depending on EOP (I2CxSTAT2[24]) and EPSZE (I2CxCON2[24]).