20.5.4.4.4 Examples Messages of Client Reception

Receiving a client message is an automatic process. The user software handling the client protocol uses the client interrupt to synchronize to the events.

When the client detects the valid address, the associated interrupt will notify the user software to expect a message. Upon receiving the data, as each data byte transfers to the I2CxRCV register, an interrupt notifies the user software to unload the buffer.

Figure 20-31 illustrates a simple receive message. Because it is a 7-bit address message, only one interrupt occurs for the address bytes. Then, interrupts occur for each of four data bytes. At an interrupt, the user software may monitor the status bits, RBF (I2CxSTAT1[1]), D/A (I2CxSTAT1[5]) and R/W (IC2xSTAT1[2]), to determine the condition of the byte received.

Figure 20-32 illustrates a similar message using a 10-bit address. In this case, two bytes are required for the address.

Figure 20-33 illustrates a case where the user software does not respond to the received byte and the buffer overruns. On reception of the second byte, the module will automatically NACK the host transmission. Generally, this causes the host to resend the previous byte. The I2COV status bit (I2CxSTAT1[6]) indicates that the buffer has overrun. The I2CxRCV register buffer retains the contents of the first byte. On reception of the third byte, the buffer is still full, and again, the module will NACK the host. After this, the user software finally reads the buffer. Reading the buffer will clear the RBF status bit; however, the I2COV status bit remains set. The user software must clear the I2COV status bit (I2CxSTAT1[6]). The next received byte is moved to the I2CxRCV register buffer and the module responds with an ACK.

Figure 20-34 highlights clock stretching while receiving data. In the previous examples, the STREN bit (I2CxCON1[6]) is equal to ‘0’, which disables clock stretching on receive messages. In this example, the user software sets STREN to enable clock stretching. When STREN = 1, the module will automatically clock stretch after each received data byte, allowing the user software more time to move the data from the buffer. If RBF = 1 at the falling edge of the ninth clock, the module automatically clears the SCLREL bit (I2CxCON1[12]) and pulls the SCLx bus line low. As shown with the second received data byte, if the user software can read the buffer and clear the RBF status bit before the falling edge of the ninth clock, the clock stretching will not occur. The user software can also suspend the bus at any time. By clearing the SCLREL bit, the module pulls the SCLx line low after it detects the bus SCLx low. The SCLx line remains low, suspending transactions on the bus until the SCLREL bit is set. See Client Reception (7-bit Address) and Client Reception (10-bit Address) for application examples.