15.3.3 ADC n Result Ready Status Flags Register

Note: Each bit in this register is set by hardware when the corresponding channel conversion result is written into ADnCHxDATA register. The bit is cleared by hardware when ADnCHxDATA register is read by software.

Table 15-7. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	ADnSTAT
Offset:	0x808, 0xA08


Bit	31	30	29	28	27	26	25	24
	CH[31:24]RDY
Access	HS/HC	HS/HC	HS/HC	HS/HC	HS/HC	HS/HC	HS/HC	HS/HC
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	CH[23:16]RDY
Access	HS/HC	HS/HC	HS/HC	HS/HC	HS/HC	HS/HC	HS/HC	HS/HC
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	CH[15:8]RDY
Access	HS/HC	HS/HC	HS/HC	HS/HC	HS/HC	HS/HC	HS/HC	HS/HC
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	CH[7:0]RDY
Access	HS/HC	HS/HC	HS/HC	HS/HC	HS/HC	HS/HC	HS/HC	HS/HC
Reset	0	0	0	0	0	0	0	0

15.3.3 ADC n Result Ready Status Flags Register

Bits 31:24 – CH[31:24]RDY Channel x Conversion Result Ready bit

Bits 23:16 – CH[23:16]RDY Channel x Conversion Result Ready bit

Bits 15:8 – CH[15:8]RDY Channel x Conversion Result Ready bit

Bits 7:0 – CH[7:0]RDY Channel x Conversion Result Ready bit